| The most exotic application of CISC-to-RISC instruction
translation might be IBM's rumored PowerPC 615 (IBM won't
confirm or deny its existence). This chip could run 80x86
software using a sophisticated decoder similar to
NexGen's, rather than the wasteful method of integrating
an 80x86 core. Instead of decoding 80x86 into RISC86,
however, it would convert 80x86 into native PowerPC
instructions. IBM already has this technology working in software. It's called the IST (Instruction-Set Translator), and it uses advanced code-analysis and caching techniques to convert 80x86 code into RISC code (see "Emulation: RISC's Secret Weapon," April BYTE). Implementing the IST in hardware could yield big performance gains and render the emulation so transparent that many users would mistake it for a native 80x86. One source told BYTE that the IST front end might be implemented in a coprocessor chip, rather than integrated with the PowerPC. There are three reasons for this: (1) it would minimize the PowerPC's die size and reduce fabrication costs; (2) it would let system vendors offer models with or without the emulation coprocessor and perhaps let users add the chip later; and (3) if Intel sues IBM over the technology and wins an injunction, sales of motherboards with the empty socket could continue, and IBM wouldn't have to pull the CPU itself off the market. Intel acknowledges that this approach to emulation could deliver near-native performance but adds that it might backfire on IBM if the performance is too good. Software developers might regard the PowerPC as just another 80x86-compatible chip and stop writing native PowerPC software. But one software developer dismissed this notion: "Even if we can get a 10 percent difference by going native, we'll go native," said Dennis Moore, director of product marketing at Oracle (Redwood Shores, CA). If IBM decides to introduce a chip like the PowerPC 615, it's expected to hit the market sometime in mid-1995. Copyright 1994-1998 BYTE |