| The high cost of R&D in creating the next wave of
CPUs and memory chips has prompted a new round of
collaborations among high-technology firms. Last summer,
IBM, Toshiba, and Siemens Nixdorf announced they had
agreed to co-develop 256-Mb chips. Currently, Texas
Instruments and Hitachi say that they, too, will share
research efforts in developing 256-Mb memory chips. And in
another alliance, AMD has hooked up with Hewlett-Packard
to share development costs and expertise in developing the
technology for a new generation of 0.35-micron chips that
could range from RAM chips to RISC processors. AMD and HP are working on a process technology capable of cramming as many as 10 million transistors on a single chip. To reach that goal, they must shrink the minimum feature size to 0.35 micron. (In contrast, the first versions of the Pentium have about 3.1 million transistors and a feature size of 0.8 micron.) While the two companies have agreed to share technology to develop the smaller submicron process, each company will use the new chip technology individually. AMD and HP hope their collaboration will result in 0.35-micron chips by late 1994, with volume shipments beginning in 1995. That's about the same time industry observers think Intel will introduce the P6. Although HP and AMD aren't releasing financial details of their alliance, the cost of developing the new submicron technology is estimated at $800 million to $1 billion, according to Charles Boucher, a senior industry analyst at Dataquest. IBM, Siemens Nixdorf, and Toshiba estimate that their development cost on the 256-Mb chip will reach about $1 billion. "The cost is enormous," Boucher said of the HP/AMD effort. "This partnership is very strategic for AMD because it will give them the means to compete with their primary competitor, which is Intel. I think it's a positive move." HP also benefits, as it can apply the submicron technology to its line of Precision Architecture RISC processors and ASICs (application-specific ICs). Copyright 1994-1997 BYTE |