| Like Intel's Pentium (formerly known as the P5),
Motorola's next-generation microprocessor will use
superscalar architecture, parallel pipelines, branch
prediction, and a common instruction pipe that the integer
and FPUs share. It will also maintain full software
compatibility with earlier members of its chip family. But
by the time Motorola's 68060 begins to ship in production
quantities, Intel's Pentium will likely have been in
production for over a year: Motorola expects to begin
manufacturing the 68060 in the first half of 1994. At Michael Slater's Microprocessor Forum last October in Burlingame, California, Motorola (Austin, TX) said that the 68060 will run about 31/2 times faster than a 25-MHz 68040, delivering about 77 MIPS at its initial clock rate of 50 MHz. That's not quite as fast as the Pentium, which Intel says will deliver about 100 MIPS at its initial frequency of 66 MHz. Motorola says it hopes to eventually drive the 68060 at 66 MHz; that version of the chip could achieve a performance of 100 MIPS. However, the 68060 contains about 2 million transistors with a minimum transistor size of 0.5 micron, compared to the Pentium's 3 million transistors in 0.8-micron technology. Also, the 68060 is a static CMOS chip that operates at 3.3 V as well as at 5 V; the first Pentium is expected to be strictly a 5-V device. Architecturally, both chips take advantage of similar techniques to wring more performance from their traditional CISC designs. In the 68060, a four-stage fetch unit dispatches integer instructions along a pair of four-stage execution pipelines. At the same time, the chip stores the instructions in a 256-entry cache and predicts upcoming branches based on past patterns. When the chip correctly predicts a branch that is taken, it effectively jumps to the new address in 0 clock cycles. When the processor correctly predicts that a branch in a program will not be taken, it jumps to the correct address in 1 clock cycle. How efficient are the parallel pipelines? Motorola says the 68060 executes 50 percent to 60 percent of the instructions in pairs. That's with integer code generated by existing compilers. Presumably, more instructions could be generated in parallel by generating code with an optimized compiler. The 68060's FPU has three arithmetic units — an adder, a multiplier, and a divider — and it shares the execution stages of the primary integer pipeline. Floating-point instructions can be dispatched along this pipeline, while integer instructions flow through the secondary pipeline; both instructions' execution cycles can overlap. Floating-point loads and stores take 1 cycle, addition takes 3 cycles, multiplication takes 4 cycles, and division takes 24 cycles. Other features of the 68060 include a pair of 8-KB caches for instructions and data, as well as a 32-bit data/address bus similar to the 68040's. If you're wondering why the new chip is called the 68060 instead of the 68050, Motorola has an explanation. Traditionally, odd-numbered chips in the 68000 family offer incremental improvements, while even-numbered chips are considered major leaps. Motorola says its customers wanted more than the small gain implied by the step from 68040 to 68050. Competition was surely a factor as well. Intel's Pentium significantly raises the stakes for CISC processors. With the 68060 expected to ship about a year after the Pentium, it's no wonder that Apple, one of Motorola's biggest customers, is adopting a new family of RISC chips for its next-generation machines. Motorola and IBM are jointly developing those chips, the PowerPC series. Copyright 1994-1997 BYTE |