| Windows NT is sparking some hot competition among chip
makers who want a piece of the growing market for
high-performance desktop PCs and servers. Three new RISC
microprocessors from DEC (Hudson, MA), Integrated Device
Technology (Santa Clara, CA), and Toshiba America (Irvine,
CA) are challenging the early leads claimed by Intel's
Pentium and the Mips R4400. All three new chips are
sampling now and are scheduled for volume production early
next year. DEC's entry is the AXP 21066, the lowest-cost member of the Alpha AXP family. The 21066 sets a new standard for integration: It's the first microprocessor to include support for PCI (Peripheral Component Interconnect). It also integrates a memory controller and a graphics accelerator. IDT and Toshiba are introducing separate versions of the new Orion R4600, developed in a joint venture with Quantum Effects Designs (San Jose, CA). The Orion is a Mips R4400-compatible CPU that is claimed to be faster than Mips's own R4400PC. IDT is producing a 5-V version while Toshiba makes a 3.3-V part. IDT says it will introduce a 3.3-V version as well in 1994. All these chips share a common design philosophy: By departing slightly from existing architectures within their respective processor families, they slash costs while delivering Pentium-level or better performance. DEC's 21066, for example, shares the same superscalar architecture as the faster AXP 21064, but it's clocked at 166 MHz instead of 200 MHz. The data bus was scaled down from 128 bits to 64 bits, and the pin count was reduced from 431 to 287. Yet despite these modifications, the level of integration was actually increased. The 21066 includes the equivalent of a complete processor-to-PCI chip set, except for a bridge chip to a secondary I/O bus. The bridge chip was omitted so that system designers can couple the 21066 to any secondary I/O bus they want, such as ISA or EISA. All this integration adds approximately 10 percent more silicon area to the core logic of the 21066. The chip is currently manufactured with the use of a three-layer-metal, 0.68-micron, CMOS process technology, but it will move to a 0.5-micron process next spring, shrinking the die almost 50 percent. The Orion R4600 similarly diverges from its parent architecture while maintaining compatibility and reducing cost. Although it's pin compatible with the Mips R4400PC, the Orion has a five-stage instead of an eight-stage pipeline, and it substitutes a two-way set-associative cache for the R4400's direct-map primary cache. IDT says these modifications result in fewer stalls during instruction processing. Another significant departure from the R4400PC is the Orion's fully static core and standby mode. A new wait instruction stops all internal clocks and dramatically cuts power usage. IDT says the 3.3-V Orion consumes only about 2.3 W when running normally, and 40 to 60 milliwatts while on standby. The Orion's die size, power dissipation, and price are about half that of the R4400PC. Yet it's fully compatible with the R4400PC and has the same 64-bit data paths. The first Orion will be clocked internally at 100 MHz and externally at 50 MHz (i.e., 100/50). Next year, faster versions are expected to range from 120/40 MHz to 133/66 MHz, topping out at an estimated 84.5 SPECint92. Of course, other chip makers aren't standing still, either. In 1994, Intel plans to move the Pentium to a 0.65-micron process that should boost its performance while sharply reducing both power consumption and manufacturing costs. IBM and Motorola hope to introduce their PowerPC 603, 604, and 620 chips by late 1994, and speedier versions of the Mips R4x00 series and DEC Alpha are anticipated as well. CPUs For Windows NT
 Copyright 1994-1997 BYTE |